1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing it, and in particular to the improvement in the surge resistance of a semiconductor device having a junction field-effect transistor (hereinafter abbreviated to J-FET).
2. Description of the Related Art
A conventional J-FET has a basic structure that comprises a P-type epitaxial layer 2 formed on a P++-conductive substrate 1; an N-type epitaxial layer 3 on the P-type epitaxial layer 2; and an N+-conductive source diffusion layer 4, an N+-conductive drain diffusion layer 5 and a P+-conductive gate diffusion layer 6 formed in the N-type epitaxial layer 3, as in FIG. 15. A P+-conductive contact diffusion layer 7 is formed, and this is connected to the gate diffusion layer 6 at a site not shown in the drawing A source electrode 10 and a drain electrode 11 are formed, and they are connected to the source diffusion layer 4 and the drain diffusion layer 5, respectively, via the holes formed in the protective insulation film 9. A gate electrode 12 is formed entirely on the back of the substrate so that this is connected to the contact diffusion layer 7 via the substrate 1 (for example, refer to JP-A 11-162993).
In the ordinary unit J-FET having the above-mentioned basic structure, the impurity concentration in the P++-conductive substrate 1 is on the order of 1020 cm−3; the impurity concentration and the thickness of the P-type epitaxial layer 2 are from 1015 cm−3 to 1016 cm−3, and from 10 μm to 20 μm, respectively; the impurity concentration and the thickness of the contact diffusion layer 7 are from 1018 cm−3 to 1020 cm−3, and from 10 μm to 30 μm, respectively; and the impurity concentration and the thickness of the N-type epitaxial layer 3 are from 1015 cm−3 to 1016 cm−3, and from 2 μm to 20 μm, respectively. The impurity concentration and the thickness of the source diffusion layer 4 and the drain diffusion layer 5 are from 1018 cm−3 to 1020 cm−3, and from 1 μm to 3 μm, respectively; the impurity concentration and the thickness of the gate diffusion layer 6 are from 1018 cm−3 to 1020 cm−3, and from 1 μm to 5 μm, respectively. Under such condition, various unit J-FETs are produced in accordance with the application of the devices comprising them.
However, the above-mentioned conventional J-FET structure has a problem in that it is electrically ruptured with some frequency owing to the high-voltage noise (hereinafter referred to as “surge voltage”) running into the source electrode 10, the drain diffusion layer 5 or the gate electrode 12 (gate diffusion layer 6) thereof from the peripheral devices around it (this will be hereinafter referred to as “surge rupture”). The surge rupture is described with reference to FIG. 16. FIG. 16 is a graphical view of the above-mentioned unit J-FET. As illustrated, the P+-conductive gate diffusion layer and contact diffusion layer and the P++-conductive substrate that are in a P-conductive region are connected to the gate electrode; while the N+-conductive source diffusion layer and drain diffusion layer that are in an N-conductive region are connected to the source electrode and the drain electrode, respectively. J-FET of the type is driven under the electric interconnection as illustrated, and when the above-mentioned surge voltage is instantaneously applied between the source diffusion layer or the drain diffusion layer and the gate diffusion layer, then a heavy current may run through the PN junction of the above-mentioned structure, and the structure especially between the source diffusion layer and the gate diffusion layer may be thereby ruptured. The surge rupture of the type occurs more frequently when the spacing distance between the source diffusion layer or the drain diffusion layer and the gate diffusion layer is narrower. Accordingly, it is difficult to reduce the spacing distance between the source diffusion layer or the drain diffusion layer and the gate diffusion layer, and this will be a bar to further increasing the density of J-FET. The problem with high-density unit J-FET applies also to J-FET-mounted integrated circuits.